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H9CCNNN8JTALAR 8Gb Ram Memory For Desktop Computers LPDDR3 BGA178 Storage

Good quality Laptop CPU Processors for sales
Good supplier and good quality. Hope we can cooperate next time!

—— Samual-Delke Technology

all the parts are good. thank you.

—— Пантелеев Валера

the parts 100% new ! Super !

—— 정훈 공-Kong

the CPU, CHIPSET are good qulity and good price.

—— Henry Tan

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H9CCNNN8JTALAR 8Gb Ram Memory For Desktop Computers LPDDR3 BGA178 Storage

China H9CCNNN8JTALAR 8Gb Ram Memory For Desktop Computers  LPDDR3  BGA178   Storage supplier

Large Image :  H9CCNNN8JTALAR 8Gb Ram Memory For Desktop Computers LPDDR3 BGA178 Storage

Product Details:

Certification: Original Parts
Model Number: H9HCNNN4KMMLHR

Payment & Shipping Terms:

Minimum Order Quantity: 1 package
Price: Negotiation
Packaging Details: 10cm X 10cm X 5cm
Delivery Time: 3-5 work days
Payment Terms: T/T, PayPal, Western Union, Escrow and others
Supply Ability: 6000pcs per month
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Detailed Product Description
Item Number: H9CCNNN8JTALAR Package: BGA178
Org.: X32 Density: 8GB
Vol:: 1.8V-1.2V-1.2V Speed: T/U
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DRAM Memory Chip H9CCNNN8JTALAR 8Gb LPDDR3 BGA178 Memory Chip Storage​

 

 

 

H9CCNNN8JTALAR

 

Features:

[ FBGA ]

  • Operation Temperature
    - -30'C ~ 105'C
  • Packcage
    - 178-ball FBGA
    - 11.0x11.5mm2, 1.00t, 0.65mm pitch
    - Lead & Halogen Free

[ LPDDR3 ]

  • VDD1 = 1.8V (1.7V to 1.95V)
  • VDD2, VDDCA and VDDQ = 1.2V (1.14V to 1.30)
  • HSUL_12 interface (High Speed Unterminated Logic 1.2V)
  • Double data rate architecture for command, address and data Bus;
    - all control and address except CS_n, CKE latched at both rising and falling edge of the clock
    - CS_n, CKE latched at rising edge of the clock
    - two data accesses per clock cycle
  • Differential clock inputs (CK_t, CK_c)
  • Bi-directional differential data strobe (DQS_t, DQS_c)
    - Source synchronous data transaction aligned to bi-directional differential data strobe (DQS_t, DQS_c)
    - Data outputs aligned to the edge of the data strobe (DQS_t, DQS_c) when READ operation
    - Data inputs aligned to the center of the data strobe (DQS_t, DQS_c) when WRITE operation
  • DM masks write data at the both rising and falling edge of the data strobe
  • Programmable RL (Read Latency) and WL (Write Latency)
  • Programmable burst length: 8
  • Auto refresh and self refresh supported
  • All bank auto refresh and per bank auto refresh supported
  • Auto TCSR (Temperature Compensated Self Refresh)
  • PASR (Partial Array Self Refresh) by Bank Mask and Segment Mask
  • DS (Drive Strength)
  • DPD (Deep Power Down)
  • ZQ (Calibration)
  • ODT (On Die Termination

 

H9CCNNN8JTALAR 8Gb Ram Memory For Desktop Computers  LPDDR3  BGA178   Storage

Contact Details
Beijing Silk Road Enterprise Management Services Co.,LTD

Contact Person: Karen.

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