HY5DU561622FTP-5 DRAM Memory Chip SDRAM Memory 256 Mbit Surface Mount 200MHz 2.4 - 2.7 V

HY5DU561622FTP-5 DRAM Memory Chip SDRAM Memory 256Mbit Surface Mount, 200MHz, 2.4 → 2.7 V

DESCRIPTION
The Hynix HY5DU561622FTP-5, -4 series are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM,
ideally suited for the point-to-point applications which requires high bandwidth.
The Hynix 16Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally
pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
• VDD, VDDQ = 2.5V + / - 0.2V for 200MHz
VDD, VDDQ = 2.6V + 0.1 / -0.2V for 250MHz
• All inputs and outputs are compatible with SSTL_2
interface
• JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
• x16 device has 2 bytewide data strobes (LDQS,
UDQS) per each x8 I/O
• Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
• Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
• All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
• Write mask byte controls by LDM and UDM
• Programmable /CAS latency 3 / 4 supported
• Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
• Internal 4 bank operations with single pulsed /RAS
• tRAS Lock-Out function supported
• Auto refresh and self refresh supported
• 8192 refresh cycles / 64ms
• Full, Half and Matched Impedance(Weak) strength
driver option controlled by EMRS