W9725G6JB25I-ND Flash Memory Chip , IC DRAM 256mb Nand Flash PARALLEL 84WBGA

Basic Information
Certification: Original Parts
Model Number: W9725G6JB25I-ND
Minimum Order Quantity: 1 package
Price: Negotiation
Packaging Details: 10cm X 10cm X 5cm
Delivery Time: 3-5 work days
Payment Terms: T/T, PayPal, Western Union, Escrow and others
Supply Ability: 6000pcs per month
Detail Information
Item Numbe: W9725G6JB25I-ND Products Category: Memory & Flash Memory
Storage Capacity: 256Mb (16M X 16) Frequency: 200MHz
VOLT: 1.7 V ~ 1.9 V Technology: SDRAM - DDR2
Temp.: -40°C ~ 95°C(TC) Package: BGA96
High Light:

nand type flash memory


flash memory controller chip

Product Description

Flash Memory Chip W9725G6JB25I-ND,IC DRAM 256M PARALLEL 84WBGA​



Basic Features
Organisation x16
Speed 400 MHz
Voltage 1.8 V
Package WBGA-84




The W9725G6JB is a 256M bits DDR2 SDRAM, organized as 4,194,304 words x 4 banks x 16 bits. This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for various applications. W9725G6JB is sorted into the following speed grades: -18, -25, 25I, 25A, 25K and -3. The -18 grade parts is compliant to the DDR2-1066 (7-7-7) specification. The -25/25I/25A/25K grade parts are compliant to the DDR2-800 (5-5-5) or DDR2-800 (6-6-6) specification (the 25I industrial grade parts which is guaranteed to support -40°C ≤ TCASE ≤ 95°C). The -3 grade parts is compliant to the DDR2-667 (5-5-5) specification.


The automotive grade parts temperature, if offered, has two simultaneous requirements: ambient temperature (TA) surrounding the device cannot be less than -40°C or greater than +95°C (for 25A), +105°C (for 25K), and the case temperature (TCASE) cannot be less than -40°C or greater than +95°C (for 25A), +105°C (for 25K). JEDEC specifications require the refresh rate to double when TCASE exceeds +85°C; this also requires use of the high-temperature self refresh option. Additionally, ODT resistance and the input/output impedance must be derated when TCASE is < 0°C or > +85°C.


All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CLK rising and NOT CLK falling). All I/Os are synchronized with a single ended DQS or differential DQS- NOT DQS pair in a source synchronous fashion.



  • Power Supply: VDD, VDDQ = 1.8 V ± 0.1V
  • Double Data Rate architecture: two data transfers per clock cycle
  • CAS Latency: 3, 4, 5, 6 and 7
  • Burst Length: 4 and 8
  • Bi-directional, differential data strobes (DQS and NOT DQS ) are transmitted / received with data
  • Edge-aligned with Read data and center-aligned with Write data
  • DLL aligns DQ and DQS transitions with clock
  • Differential clock inputs (CLK and NOT CLK )
  • Data masks (DM) for write data
  • Commands entered on each positive CLK edge, data and data mask are referenced to both edges of DQS
  • Posted NOT CAS programmable additive latency supported to make command and data bus efficiency
  • Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
  • Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality
  • Auto-precharge operation for read and write bursts
  • Auto Refresh and Self Refresh modes
  • Precharged Power Down and Active Power Down
  • Write Data Mask
  • Write Latency = Read Latency - 1 (WL = RL - 1)
  • Interface: SSTL_18
  • Packaged in WBGA 84 Ball (8X12.5 mm²), using Lead free materials with RoHS compliant






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