| Certification: | ORIGINAL PARTS |
|---|---|
| Model Number: | J3455 |
| Minimum Order Quantity: | 1 piece |
| Price: | Negociation |
| Packaging Details: | Tray, 15cm X 15cm X 10cm |
| Payment Terms: | T/T, PayPal, Western Union, Escrow and others |
| Supply Ability: | 500pcs/month |
| Processor No.: | J3455 | Product Collection: | Intel Celeron Processor J Series |
|---|---|---|---|
| Code Name: | Products Formerly Apollo Lake | Vertical Segment: | Desktop |
| Status: | Launched | Launch Date: | Q3'16 |
| Lithography: | 14nm | Use Condition: | Desktop/Industrail PC |
| High Light: | computer cpu processor,multi core processor |
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Celeron Processor J3455 Desktop CPU 2M Cache, up to 2.3 GHz
Celeron J3455 is a quad-core 64-bit x86 desktop microprocessor introduced by Intel in 2016. The processor is based on Goldmont microarchitecture and is manufactured on a 14 nm process. The chip operates at 1.5 GHz with burst frequency of 2.3 GHz and has a TDP of 10 W. This MPU incorporates Intel's HD Graphics 500 GPU operating at 250 MHz with a burst frequency of 750 MHz.
| Processor number | J3455 |
| Family | Celeron |
| Technology (micron) | 0.014 |
| Processor speed (GHz) | 1.5 |
| L2 cache size (KB) | 2048 |
| The number of cores | 4 |
| EM64T | Supported |
| HyperThreading technology | Not supported |
| Virtualization technology | Supported |
| Enhanced SpeedStep technology | Supported |
| Execute-Disable bit feature | Supported |
General information:
| Type | System-on-a-Chip | ||||||
| Market segment | Desktop | ||||||
| Family |
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| Model number | J3455 | ||||||
| SoC part number |
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| Frequency | 1500 MHz | ||||||
| Maximum turbo frequency | 2300 MHz (1 core) 2200 MHz (2 or more cores) |
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| Low power frequency | 800 MHz | ||||||
| Package | 1296-ball Flip Chip Ball Grid Array (Type 3) | ||||||
| Socket | BGA1296 | ||||||
| Size | 1.22" x 0.94" / 3.1cm x 2.4cm | ||||||
| Introduction date | August 30, 2016 | ||||||
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Architecture / Microarchitecture:
| Microarchitecture | Goldmont |
| Processor core | Apollo Lake |
| Core stepping | B1 (SR2Z9) |
| Manufacturing process | 0.014 micron |
| Data width | 64 bit |
| The number of CPU cores | 4 |
| The number of threads | 4 |
| Floating Point Unit | Integrated |
| Level 1 cache size | 4 x 32 KB 8-way set associative instruction caches 4 x 24 KB 6-way set associative data caches |
| Level 2 cache size | 2 x 1 MB 16-way set associative shared caches |
| Level 3 cache size | None |
| Physical memory | 8 GB |
| Multiprocessing | Uniprocessor |
| Extensions and Technologies |
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| Security Features |
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| Low power features |
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Integrated peripherals / components:
| Display controller |
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| Integrated graphics | GPU Type: Intel HD 500 Microarchitecture: Gen 9 LP Execution units: 12 Base frequency (MHz): 250 Maximum frequency (MHz): 750 |
| Memory controller | The number of controllers: 1 Memory channels: 2 Channel width (bits): 64 Supported memory: DDR3L-1333, DDR3L-1600, DDR3L-1866, LPDDR3-1333, LPDDR3-1600, LPDDR3-1866, LPDDR4-1600, LPDDR4-2133, LPDDR4-2400 Maximum memory bandwidth (GB/s): 38.4 |
| Other peripherals |
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| Supported interfaces |
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Electrical / Thermal parameters:
| Maximum operating temperature | 105°C |
| Thermal Design Power | 10 Watt |
